1. Field
The present invention relates in general to the field of electronic design automation (EDA) tools for integrated or electronic circuits wiring design. In particular, this invention provides the capability for EDA tools to effectively deal with accessing ports and/or pins of the integrated or electronic circuits (IC). More particularly, the present invention relates to a method and/or electronic design automation (EDA) tool for creating a layout for design representation of an electronic circuit with at least one port, and a corresponding port for an integrated or electronic circuit. Still more particularly, the present invention relates to a data processing program and a computer program product for creating a layout for design representation of an electronic circuit with at least one port.
2. Description of the Related Art
The following definitions apply throughout the following specification. An electronic circuit is an element which may be used multiple times on an IC. It is typically an element of a technology circuit library. A net represents a connection which must be made between sets of source and sink pins on an IC. A wire is a set of connected conductors which form the connection represented by a net. A wire segment is a contiguous region of a single conducting layer of an IC which is a portion of a wire. A via is a conductor which forms a connection between different conducting layers of an IC, and which is a portion of a wire. A pin or port is a conducting region of a circuit instance to which a wire is connected.
In the U.S. Pat. No. 6,308,302 “Semiconductor wiring technique for reducing electromigration” by International Business Machines Corporation, a method and system of improving upon effects of electromigration on Integrated Circuits (IC) are disclosed. The disclosed method uses an optimized width of wires for interconnection of pins. Further, capacitive targets are utilized for controlling the current density. The method of categorizing nets based on width of wires, and considering RC delay of the circuit for improving upon the timing of circuit, takes as input a netlist which describes the circuits to be implemented on the IC and the interconnections between them. Each item in the netlist is defined in the circuit library which is accessible by any tool in the design tool. The categories of nets that are known by the designer to require special electromigration treatment, if any, such as high fan-out nets, are obtained. The nets are then sorted into categories based on discrete wire widths.
In the U.S. Pat. No. 7,131,096 “Method of automatically routing nets according to current density rules” by Pulsic Limited, a method and system of automatically routing interconnections within an Integrated Circuit (IC) based on current density rules are disclosed. The method includes varying size of nets based on the current density requirements. Further, utilizing a timing engine to determine paths having the least timing delay for critical nets is also disclosed. The method of determining paths having the least timing delay for critical nets in an IC via a timing engine is disclosed as a technique which automatically route interconnections of an integrated circuit while taking into consideration current density rules.
In the paper “FPGA Design Automation: A Survey” by Deming Chen et al, Foundations and Trends in Electronic Design Automation Vol. 1, No 3 (November 2006) 195-330c, a method of assigning weights to multiple nets in an IC layout based on timing criticality of nets for avoiding slacks and routing resources based on these weights is disclosed. Timing constraints are typically specified as the maximum path delay constraints from the primary inputs and/or FF outputs to primary outputs and/or FF inputs. Given a mapped and placed circuit, one can perform static timing analysis to compute the signal arrival times and required times at every pin in the design, and then compute the slack at every pin and every source-sink pair in each net. The nets with smaller slacks are more critical. The simplest form of timing optimization is to order the nets by their timing criticality, so that timing-critical nets are routed first to avoid long detours.
The prior art is disclosing a method of categorizing nets based on width of wires and considering RC delay of the circuit for improving upon the timing of circuit, and a method of determining paths having least timing delay for critical nets in an IC via a timing engine.
In the prior art, pin or port shapes get defined to allow routing access under all circumstances, therefore the port size is larger than necessary. Different connection points to the port lead to different resistive paths leading to different timing rules. The timing rules must guard band non-optimal connections. The correct timing can be determined only after routing and extraction, when the connection to the pin is known.